Re: [edk2-devel] [PATCH edk2-platforms v2 0/3] SbsaQemu: support multiple PCI Express buses

["Gerd Hoffmann" <kraxel@redhat.com>]

On Tue, Jun 04, 2024 at 09:23:30AM GMT, Marcin Juszkiewicz wrote:
> W dniu 28.05.2024 o 16:31, Ard Biesheuvel pisze:
> > I would expect each host bridge to have its own separate resource
> > windows for config space, buses and MMIO regions.

That isn't how qemu pxb-pcie host bridge works on x86 though.  It does
*not* create a separate pci domain and resources such as bus numbers are
shared.

> OK. I have to admit that I never checked how physical NUMA system handles
> PCI Express. The code in patches was done by comparing with other QEMU
> targets.

It's probably not that easy.  On x86 initialization works like this:

 (1) the firmware sets up bridge windows and pci bars.
 (2) qemu generates acpi tables with matching _CRS ranges.
 (3) the firmware downloads and installs the acpi tables.

On arm qemu does the resource allocation for the root bridge windows and
communicates them to the firmware via FDT, so stealing ideas from x86
probably isn't going to work very well.

I think one option would be to have the firmware split the ranges it
got and distribute them across the root bridges, program the root
windows accordingly, generate acpi tables accordingly.

Going for a separate pci domain with separate ecam and separate bus
namespace and separate mmio ressources should be possible too, but that
most likely will need a bunch of changes on the qemu side.

HTH & take care,
  Gerd



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