From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id C237F9417DF for ; Tue, 4 Jun 2024 12:07:03 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Iizd5nSkB3CcnRMEy+nOgOgi2rKJuJk5JiQrHqvSMgM=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition:Content-Transfer-Encoding; s=20240206; t=1717502823; v=1; b=UkLquSnG0vCV8m57MSiVBp9LC+IrWAgMjHQTUOIIp6i/9L/xKHBlT4Srnq8UuaseySXiwsYy PMoBBIHYXFYvi3yb+FVgPtJiDR7GcI6V6UlJxT+Tydd7zS9WjUrQU56ovMXhLYrl7C6sDw9KtQI kVuRceSkZgVKcVas/JpVyafguD1zNhXaTkO2V1cimdcL5vHZFkCMSytX8VsW2KptG9Ru7PCcIfA gqYmfl/mwSUbMMWBW2BpqNDNdJL1vRSYZlY+xN4j9CDfk/lKj5A/SHdjZJr0MT3Hrb9bi+cFe/F CLfw3+fvP9a9P2IesaRNVcz+dqAfAKxc/1HofRPfVkuMA== X-Received: by 127.0.0.2 with SMTP id 41VIYY7687511xaSfJUmbSTu; Tue, 04 Jun 2024 05:07:02 -0700 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web10.19790.1717502821689164809 for ; Tue, 04 Jun 2024 05:07:01 -0700 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-195-iaEfPvuWNTeIUQbugOuDiw-1; Tue, 04 Jun 2024 08:06:57 -0400 X-MC-Unique: iaEfPvuWNTeIUQbugOuDiw-1 X-Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9DA2F805980; Tue, 4 Jun 2024 12:06:56 +0000 (UTC) X-Received: from sirius.home.kraxel.org (unknown [10.39.192.217]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6D3541C060A4; Tue, 4 Jun 2024 12:06:56 +0000 (UTC) X-Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 0A917180098E; Tue, 4 Jun 2024 14:06:55 +0200 (CEST) Date: Tue, 4 Jun 2024 14:06:54 +0200 From: "Gerd Hoffmann" To: devel@edk2.groups.io, marcin.juszkiewicz@linaro.org Cc: Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Ray Ni Subject: Re: [edk2-devel] [PATCH edk2-platforms v2 0/3] SbsaQemu: support multiple PCI Express buses Message-ID: References: <20240528-review-multiple-pcie-0425-v2-0-e2ec9f098a78@linaro.org> <64916d39-c895-48a5-af9a-655c57233300@linaro.org> MIME-Version: 1.0 In-Reply-To: <64916d39-c895-48a5-af9a-655c57233300@linaro.org> X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 04 Jun 2024 05:07:01 -0700 Resent-From: kraxel@redhat.com Reply-To: devel@edk2.groups.io,kraxel@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: l9RRmfzydcKu8TjQ7RLQz8aOx7686176AA= Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=UkLquSnG; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io On Tue, Jun 04, 2024 at 09:23:30AM GMT, Marcin Juszkiewicz wrote: > W dniu 28.05.2024 o 16:31, Ard Biesheuvel pisze: > > I would expect each host bridge to have its own separate resource > > windows for config space, buses and MMIO regions. That isn't how qemu pxb-pcie host bridge works on x86 though. It does *not* create a separate pci domain and resources such as bus numbers are shared. > OK. I have to admit that I never checked how physical NUMA system handles > PCI Express. The code in patches was done by comparing with other QEMU > targets. It's probably not that easy. On x86 initialization works like this: (1) the firmware sets up bridge windows and pci bars. (2) qemu generates acpi tables with matching _CRS ranges. (3) the firmware downloads and installs the acpi tables. On arm qemu does the resource allocation for the root bridge windows and communicates them to the firmware via FDT, so stealing ideas from x86 probably isn't going to work very well. I think one option would be to have the firmware split the ranges it got and distribute them across the root bridges, program the root windows accordingly, generate acpi tables accordingly. Going for a separate pci domain with separate ecam and separate bus namespace and separate mmio ressources should be possible too, but that most likely will need a bunch of changes on the qemu side. HTH & take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#119445): https://edk2.groups.io/g/devel/message/119445 Mute This Topic: https://groups.io/mt/106345969/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-