Hi Lingheng Du,

What is the use of adding this header file and how did you create it? I
think EDK2 needs ACPI spec to be released to get these definitions
added. Also, these are not part of 6.5 and hence names like
EFI_ACPI_6_5* are incorrect. So, it will be helpful if you add some
commit message why do we need this header.

Thanks,
Sunil
On Mon, Apr 29, 2024 at 05:53:55PM +0800, gaoliming via groups.io wrote:
> From: dylanlhdu <dylanlhdu@tencent.com>
>
>         Signed-off-by: Lingheng Du <dylanlhdu@tencent.com>
>         Reviewed-by: Song Huang  <vicshuang@tencent.com>
>         Reviewed-by: Bing Fan <tombinfan@tencent.com>
> ---
>  .../Include/IndustryStandard/AcpiRiscv64.h    | 176 ++++++++++++++++++
>  1 file changed, 176 insertions(+)
>  create mode 100644 edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h
>
> diff --git a/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h b/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h
> new file mode 100644
> index 00000000..4111b3ea
> --- /dev/null
> +++ b/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h
> @@ -0,0 +1,176 @@
> +/** @file
> +  RISCV64 platform ACPI related support April, 2022.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef ACPI_RISCV64_H_
> +#define ACPI_RISCV64_H_
> +
> +//
> +// Ensure proper structure formats
> +//
> +#pragma pack(1)
> +
> +///
> +/// RISC-V Interrupt Type
> +///
> +#define EFI_ACPI_6_5_INC_RINTC_TYPE  0x18
> +#define EFI_ACPI_6_5_INC_IMSIC_TYPE  0x19
> +#define EFI_ACPI_6_5_INC_APLIC_TYPE  0x1A
> +#define EFI_ACPI_6_5_INC_PLIC_TYPE   0x1B
> +
> +///
> +///  RISC-V Interrupt Controller (RINTC)
> +///
> +typedef struct {
> +  UINT8     Type;
> +  UINT8     Length;
> +  UINT8     Version;
> +  UINT8     Reserved;
> +  UINT32    Flags;
> +  UINT64    HartId;
> +  UINT32    Uid;
> +  UINT32    ExtIntcId;
> +  UINT64    ImsicAddr;
> +  UINT32    ImsicSize;
> +} EFI_ACPI_6_5_INC_RINTC_STRUCTURE;
> +
> +///
> +///  Incoming MSI Controller (IMSIC)
> +///
> +typedef struct {
> +  UINT8     Type;
> +  UINT8     Length;
> +  UINT8     Version;
> +  UINT8     Reserved;
> +  UINT32    Flags;
> +  UINT16    NumIds;
> +  UINT16    NumGuestIds;
> +  UINT8     GuestIndexBits;
> +  UINT8     HartIndexBits;
> +  UINT8     GroupIndexBits;
> +  UINT8     GroupIndexShift;
> +} EFI_ACPI_6_5_INC_IMSIC_STRUCTURE;
> +
> +///
> +///  RISC-V Advanced Platform Level Interrupt Controller (APLIC)
> +///
> +typedef struct {
> +  UINT8     Type;
> +  UINT8     Length;
> +  UINT8     Version;
> +  UINT8     AplicId;
> +  UINT32    Flags;
> +  UINT8     HW_ID[8];
> +  UINT16    NumIdc;
> +  UINT16    ExternSoureceSupport;
> +  UINT32    GSysInterruptBase;
> +  UINT64    AplicAddress;
> +  UINT32    AplicSize;
> +} EFI_ACPI_6_5_INC_APLIC_STRUCTURE;
> +
> +///
> +///   RISC-V Platform Level Interrupt Controller (PLIC)
> +///
> +typedef struct {
> +  UINT8     Type;
> +  UINT8     Length;
> +  UINT8     Version;
> +  UINT8     PlicId;
> +  UINT8     HwId[8];
> +  UINT16    NumIrqs;
> +  UINT16    MaxPrio;
> +  UINT32    Flags;
> +  UINT32    PlicSize;
> +  UINT64    PlicAddress;
> +  UINT32    GsiBase;
> +} EFI_ACPI_6_5_INC_PLIC_STRUCTURE;
> +
> +///
> +/// RISC-V Hart Capabilities Table (RHCT)
> +///
> +typedef struct {
> +  EFI_ACPI_DESCRIPTION_HEADER    Header;
> +} EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
> +
> +///
> +/// RHCT Revision
> +///
> +#define EFI_ACPI_6_5_RHCT_APIC_DESCRIPTION_TABLE_REVISION  0x05
> +
> +///
> +/// RHCT types
> +///
> +#define EFI_ACPI_6_5_NODE_ISA_TYPE       0x0
> +#define EFI_ACPI_6_5_NODE_CM0_TYPE       0x1
> +#define EFI_ACPI_6_5_NODE_MMU_TYPE       0x2
> +#define EFI_ACPI_6_5_NODE_RESERVED_TYPE  0x3
> +#define EFI_ACPI_6_5_NODE_HART_TYPE      0xFFFF
> +
> +///
> +/// RHCT Flags
> +///
> +#define ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU  (1)
> +
> +///
> +/// ISA string node
> +///
> +typedef struct {
> +  UINT16    Type;
> +  UINT16    Length;
> +  UINT16    Revision;
> +  UINT16    IsaLength;
> +  UINT8     IsaString[];
> +} EFI_ACPI_6_5_NODE_ISA_STRING_STRUCTURE;
> +
> +///
> +/// CM0 node
> +///
> +typedef struct {
> +  UINT16    Type;
> +  UINT16    Length;
> +  UINT16    Revision;
> +  UINT8     Reserved;
> +  UINT8     CbomSize;
> +  UINT8     CbopSize;
> +  UINT8     CbozSize;
> +} EFI_ACPI_6_5_NODE_CM0_STRUCTURE;
> +
> +///
> +/// MMU node
> +///
> +typedef struct {
> +  UINT16    Type;
> +  UINT16    Length;
> +  UINT16    Revision;
> +  UINT8     Reserved;
> +  UINT8     MmuType;
> +} EFI_ACPI_6_5_NODE_MMU_STRUCTURE;
> +
> +///
> +/// MMU type
> +///
> +#define EFI_ACPI_6_5_MMU_SV39_TYPE  0x0
> +#define EFI_ACPI_6_5_MMU_SV48_TYPE  0x1
> +#define EFI_ACPI_6_5_MMU_SV57_TYPE  0x2
> +
> +///
> +/// Hart Info Node
> +///
> +typedef struct {
> +  UINT16    Type;
> +  UINT16    Length;
> +  UINT16    Revision;
> +  UINT16    NumOffsets;
> +  UINT32    Uid;
> +} EFI_ACPI_6_5_NODE_HARTINFO_STRUCTURE;
> +
> +///
> +/// "RHCT" RISC-V Hart Capabilities Table
> +///
> +#define EFI_ACPI_6_5_RHCT_HART_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'H', 'C', 'T')
> +
> +#pragma pack()
> +
> +#endif
> \ No newline at end of file
> --
> 2.34.1
>
>
>
>
>
>
>