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From: "Gerd Hoffmann" <kraxel@redhat.com>
To: Dun Tan <dun.tan@intel.com>
Cc: devel@edk2.groups.io, Ray Ni <ray.ni@intel.com>,
	 Laszlo Ersek <lersek@redhat.com>,
	Rahul Kumar <rahul1.kumar@intel.com>
Subject: Re: [edk2-devel] [Patch V3] UefiCpuPkg:Limit PhysicalAddressBits in special case
Date: Thu, 11 Jan 2024 11:21:13 +0100	[thread overview]
Message-ID: <wnx5k2y4nzh6pqrky6m2cp5hyomhqaeg7iwrtczvrb6xxwf6rv@lyse2c4whsgz> (raw)
In-Reply-To: <20240111085947.1105-1-dun.tan@intel.com>

On Thu, Jan 11, 2024 at 04:59:47PM +0800, Dun Tan wrote:
> When creating smm page table, limit maximum
> supported physical address bits returned by
> CalculateMaximumSupportAddress() to 47 if
> 5-Level Paging is disabled.
> When 5-Level Paging is disabled and the
> PhysicalAddressBits retrived from CPU HOB or
> CpuId is bigger than 47, and since virtual
> addresses are sign-extended, only [0, 2^47-1]
> range in 52-bit physical address is mapped
> in page table.

> +  //
> +  // Only [0, 2^47 -1] in 52-bit physical addresses is mapped in page table
> +  // when 5-Level Paging is disabled.
> +  //
> +  ASSERT (PhysicalAddressBits <= 52);
> +  if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 47)) {
> +    PhysicalAddressBits = 47;
> +  }

The code change is fine but the comment should be more verbose and
explain the why 47 not 48 is used here.  The discussion on the patch
clearly showed that the technical background is not obvious ...

take care,
  Gerd



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  reply	other threads:[~2024-01-11 10:21 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-11  8:59 [edk2-devel] [Patch V3] UefiCpuPkg:Limit PhysicalAddressBits in special case duntan
2024-01-11 10:21 ` Gerd Hoffmann [this message]
2024-01-12  1:10   ` duntan
     [not found] <17A93F5DE0125DA4.28944@groups.io>
2024-01-11  9:07 ` duntan

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